Discussion:
[edk2] Mapping global variables to R/W memory during In Place execution
Arora Sakar
2015-06-19 10:45:23 UTC
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Hi

The UEFI boot flow on my ARMv8 machine, starts with in place execution on NOR flash, with DDR uninitialized. The initial code has some global variables which need to be modified at run time. I need to map these variables on to a read/write memory like an OCRAM or SRAM, so that they can be used by the intermediate code till the complete UEFI code is relocated to DDR memory. What approach should be taken to make this work?

Please point to an example that is doing anything similar to this.

Thanks
Sakar

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Andrew Fish
2015-06-19 16:13:15 UTC
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Post by Arora Sakar
Hi
The UEFI boot flow on my ARMv8 machine, starts with in place execution on NOR flash, with DDR uninitialized. The initial code has some global variables which need to be modified at run time. I need to map these variables on to a read/write memory like an OCRAM or SRAM, so that they can be used by the intermediate code till the complete UEFI code is relocated to DDR memory. What approach should be taken to make this work?
This form is not used. There are a couple of reasons.
1) This is not supported on all compilers (I don’t think it is supported by VC++). I know gcc supports linker scripts that allow different addresses to be assigned to different sections. So text (Code) can point to the ROM, and data points to SRAM.
2) The PEIM phase is made up of multiple modules, PEIM, that are NOT linked tighter, so this would require some way to make sure the global data was allocated correctly to the different modules.
3) The PEIMs are all linked a zero when they get built, and when they get placed in the FV they are relocated to the XIP (eXecute In Place). This makes using a linker script very hard, maybe impossible.

The common boot flow for PI is:
1) SEC sets up temp RAM and passes it into the PEI Core to use.
a) This means you can write C code as there is stack, and the PEI Core gets heap.
b) For x86 the temp RAM is the cache setup to work like RAM
c) For SoCs this is usually SRAM (or OCRAM as you point out).
2) A PEIM turns on memory and calls the PEI Core
3) PEI Core migrates stack and heap to new permanent memory.

The common way that PEIMs remember is to use a HOB.

If the PEIM runs later in the boot flow it is possible to have a Depex on gEfiPeiMemoryDiscoveredPpiGuid, and then you can assume globals will work in the code. This means the PEIM will get dispatched after memory gets discovered so it will get shadowed into memory.
Post by Arora Sakar
Please point to an example that is doing anything similar to this.
I don’t know of any with globals.

You can git grep for BuildGuidHob()/GetFirstGuidHob() to see the way PI PEIMs do it.

Thanks,

Andrew Fish
Post by Arora Sakar
Thanks
Sakar
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