Guo Dong
2015-06-02 13:42:30 UTC
This patch corrects a word typo and a comment error.
It also rename a label to match its function name.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Guo Dong <***@intel.com>
---
IntelFspPkg/FspSecCore/Ia32/FspApiEntry.asm | 10 +++++-----
IntelFspPkg/FspSecCore/SecMain.c | 2 +-
IntelFspPkg/Library/BaseCacheLib/CacheLib.c | 2 +-
3 files changed, 7 insertions(+), 7 deletions(-)
diff --git a/IntelFspPkg/FspSecCore/Ia32/FspApiEntry.asm b/IntelFspPkg/FspSecCore/Ia32/FspApiEntry.asm
index d0e56b2..71e3e5a 100644
--- a/IntelFspPkg/FspSecCore/Ia32/FspApiEntry.asm
+++ b/IntelFspPkg/FspSecCore/Ia32/FspApiEntry.asm
@@ -366,37 +366,37 @@ TempRamInitApi PROC NEAR PUBLIC
; Check Parameter
;
mov eax, dword ptr [esp + 4]
cmp eax, 0
mov eax, 80000002h
- jz NemInitExit
+ jz TempRamInitExit
;
; Sec Platform Init
;
CALL_MMX SecPlatformInit
cmp eax, 0
- jnz NemInitExit
-
+ jnz TempRamInitExit
+
; Load microcode
LOAD_ESP
CALL_MMX LoadMicrocode
SXMMN xmm6, 3, eax ;Save microcode return status in ECX-SLOT 3 in xmm6.
;@note If return value eax is not 0, microcode did not load, but continue and attempt to boot.
; Call Sec CAR Init
LOAD_ESP
CALL_MMX SecCarInit
cmp eax, 0
- jnz NemInitExit
+ jnz TempRamInitExit
LOAD_ESP
CALL_MMX EstablishStackFsp
LXMMN xmm6, eax, 3 ;Restore microcode status if no CAR init error from ECX-SLOT 3 in xmm6.
-NemInitExit:
+TempRamInitExit:
;
; Load EBP, EBX, ESI, EDI & ESP from XMM7 & XMM6
;
LOAD_REGS
ret
diff --git a/IntelFspPkg/FspSecCore/SecMain.c b/IntelFspPkg/FspSecCore/SecMain.c
index 63376e9..62d002b 100644
--- a/IntelFspPkg/FspSecCore/SecMain.c
+++ b/IntelFspPkg/FspSecCore/SecMain.c
@@ -102,11 +102,11 @@ SecStartup (
IdtDescriptor.Limit = (UINT16)(sizeof (IdtTableInStack.IdtTable) - 1);
AsmWriteIdtr (&IdtDescriptor);
//
- // Iniitalize the global FSP data region
+ // Initalize the global FSP data region
//
FspGlobalDataInit (&PeiFspData, BootLoaderStack, (UINT8)ApiIdx);
//
// Update the base address and length of Pei temporary memory
diff --git a/IntelFspPkg/Library/BaseCacheLib/CacheLib.c b/IntelFspPkg/Library/BaseCacheLib/CacheLib.c
index 1a08918..b38dce3 100644
--- a/IntelFspPkg/Library/BaseCacheLib/CacheLib.c
+++ b/IntelFspPkg/Library/BaseCacheLib/CacheLib.c
@@ -43,11 +43,11 @@ SearchForExactMtrr (
Check if CacheType match current default setting.
@param[in] MemoryCacheType input cache type to be checked.
@retval TRUE MemoryCacheType is default MTRR setting.
- @retval TRUE MemoryCacheType is NOT default MTRR setting.
+ @retval FALSE MemoryCacheType is NOT default MTRR setting.
**/
BOOLEAN
IsDefaultType (
IN EFI_MEMORY_CACHE_TYPE MemoryCacheType
);
It also rename a label to match its function name.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Guo Dong <***@intel.com>
---
IntelFspPkg/FspSecCore/Ia32/FspApiEntry.asm | 10 +++++-----
IntelFspPkg/FspSecCore/SecMain.c | 2 +-
IntelFspPkg/Library/BaseCacheLib/CacheLib.c | 2 +-
3 files changed, 7 insertions(+), 7 deletions(-)
diff --git a/IntelFspPkg/FspSecCore/Ia32/FspApiEntry.asm b/IntelFspPkg/FspSecCore/Ia32/FspApiEntry.asm
index d0e56b2..71e3e5a 100644
--- a/IntelFspPkg/FspSecCore/Ia32/FspApiEntry.asm
+++ b/IntelFspPkg/FspSecCore/Ia32/FspApiEntry.asm
@@ -366,37 +366,37 @@ TempRamInitApi PROC NEAR PUBLIC
; Check Parameter
;
mov eax, dword ptr [esp + 4]
cmp eax, 0
mov eax, 80000002h
- jz NemInitExit
+ jz TempRamInitExit
;
; Sec Platform Init
;
CALL_MMX SecPlatformInit
cmp eax, 0
- jnz NemInitExit
-
+ jnz TempRamInitExit
+
; Load microcode
LOAD_ESP
CALL_MMX LoadMicrocode
SXMMN xmm6, 3, eax ;Save microcode return status in ECX-SLOT 3 in xmm6.
;@note If return value eax is not 0, microcode did not load, but continue and attempt to boot.
; Call Sec CAR Init
LOAD_ESP
CALL_MMX SecCarInit
cmp eax, 0
- jnz NemInitExit
+ jnz TempRamInitExit
LOAD_ESP
CALL_MMX EstablishStackFsp
LXMMN xmm6, eax, 3 ;Restore microcode status if no CAR init error from ECX-SLOT 3 in xmm6.
-NemInitExit:
+TempRamInitExit:
;
; Load EBP, EBX, ESI, EDI & ESP from XMM7 & XMM6
;
LOAD_REGS
ret
diff --git a/IntelFspPkg/FspSecCore/SecMain.c b/IntelFspPkg/FspSecCore/SecMain.c
index 63376e9..62d002b 100644
--- a/IntelFspPkg/FspSecCore/SecMain.c
+++ b/IntelFspPkg/FspSecCore/SecMain.c
@@ -102,11 +102,11 @@ SecStartup (
IdtDescriptor.Limit = (UINT16)(sizeof (IdtTableInStack.IdtTable) - 1);
AsmWriteIdtr (&IdtDescriptor);
//
- // Iniitalize the global FSP data region
+ // Initalize the global FSP data region
//
FspGlobalDataInit (&PeiFspData, BootLoaderStack, (UINT8)ApiIdx);
//
// Update the base address and length of Pei temporary memory
diff --git a/IntelFspPkg/Library/BaseCacheLib/CacheLib.c b/IntelFspPkg/Library/BaseCacheLib/CacheLib.c
index 1a08918..b38dce3 100644
--- a/IntelFspPkg/Library/BaseCacheLib/CacheLib.c
+++ b/IntelFspPkg/Library/BaseCacheLib/CacheLib.c
@@ -43,11 +43,11 @@ SearchForExactMtrr (
Check if CacheType match current default setting.
@param[in] MemoryCacheType input cache type to be checked.
@retval TRUE MemoryCacheType is default MTRR setting.
- @retval TRUE MemoryCacheType is NOT default MTRR setting.
+ @retval FALSE MemoryCacheType is NOT default MTRR setting.
**/
BOOLEAN
IsDefaultType (
IN EFI_MEMORY_CACHE_TYPE MemoryCacheType
);
--
1.9.5.msysgit.0
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1.9.5.msysgit.0
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